Capacitive sensing

ABSTRACT

A capacitive sensing system includes a controller, a node connected to one side of a capacitance, the controller configured to measure the capacitance by measuring a time for a voltage across the capacitance to reach a predetermined reference voltage, a noise measurement circuit configured to measure electrical noise on the node, and the controller receiving the measurement of noise from the noise measurement circuit.

This application is a continuation of U.S. patent application Ser. No. 16/048,559, filed on Jul. 30, 2018, which is a continuation of U.S. patent application Ser. No. 14/189,461, filed on Feb. 25, 2014, now U.S. Pat. No. 10,060,959, which claims priority to U.S. Provisional Application No. 61/770,116, filed on Feb. 27, 2013, each of which is hereby incorporated herein by reference in its entirety. This application is related to co-pending U.S. patent application Ser. No. 14/189,447 entitled “Capacitive Sensing”, filed on Feb. 25, 2014, now U.S. Pat. No. 9,846,185, with the same inventorship and same assignee as this application.

BACKGROUND

Capacitive sensing measures a capacitance resulting from two or more conductive surfaces separated by a dielectric. Capacitive sensing is commonly used to detect a change in capacitance resulting from the proximity of a human hand, a touch of a human finger, or a touch of a conductive stylus. Capacitive sensing is commonly used for human interfacing with electronic systems, for example; mobile phones, tablet computers, electronic games, electronic instruments, appliances, automotive systems, and industrial systems.

There are many alternative methods for capacitive sensing. For example, a capacitance may be measured by using the capacitance in an oscillator and measuring the frequency of oscillation. Alternatively, a capacitance may be measured by measuring the attenuation of an AC signal. Alternatively, a capacitance can be measured by measuring the time required to charge the capacitance through a known resistance. Each alternative measurement method has inherent advantages, limitations and tradeoffs involving accuracy, cost, response-time, and so forth. In general, capacitive measurement circuits are affected by temperature, humidity, and electrical noise. There is an ongoing need for improved capacitive sensing.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a block diagram schematic of an example capacitive sensing system.

FIG. 1B is a timing diagram for a voltage waveform in the capacitive sensing system of FIG. 1A.

FIG. 2A is a block diagram schematic of an example alternative embodiment of the capacitive sensing system of FIG. 1A.

FIG. 2B is a timing diagram for an example voltage waveform in the capacitive sensing system of FIG. 2A.

FIG. 2C is a timing diagram for an alternative example voltage waveform in the capacitive sensing system of FIG. 2A.

FIG. 2D is a timing diagram for an alternative example voltage waveform in the capacitive sensing system of FIG. 2A.

FIG. 3A is a block diagram schematic of an example embodiment of a noise detection circuit in the system of FIG. 2A.

FIG. 3B is a block diagram schematic of an example embodiment of an alternative noise detection circuit in the system of FIG. 2A.

FIG. 4A is a block diagram of an alternative example embodiment of the capacitive sensing systems of FIGS. 1A and 2A.

FIG. 4B is a timing diagram for an example voltage waveform in the capacitive sensing system of FIG. 4A.

FIG. 5 is a flow chart illustrating an example embodiment of a method for capacitive sensing.

DETAILED DESCRIPTION

FIG. 1A is a simplified block diagram of an example system 100 for illustrating some basic principles for one particular method for capacitive sensing. In the example of FIG. 1, a change in capacitance is measured by measuring the time required to charge or discharge the capacitance. In FIG. 1, a conductive capacitive plate 102 is separated from electrical ground by a dielectric 104. The dielectric 104 may be, for example, glass or air. An object 106 (for example, a human, depicted by an unknown variable resistance) provides a conductive path from the dielectric 104 to ground. There is an effective variable capacitance C_(t) formed by the conductive plate 102, the dielectric 104, and the object 106. N₁ designates the node connecting the conductive plate 102 to the remaining circuitry. A switch 108 couples node N₁ to a voltage V or to ground. A capacitance C may be, for example, the total line capacitance resulting from all conductive traces connected to node N₁. Likewise, a resistance R may be the total resistance between the source of the voltage V and node N₁ (for example, the resistance of conductive traces and the resistance of switch 108).

The switch 108 is controlled by a timer/controller 112. When the switch 108 switches to the voltage V, the parallel capacitances (C and C_(t)) start charging. A comparator 110 compares the voltage at node N₁ to a high reference voltage VREF_(HI) and to a low reference voltage VREF_(LO). The timer/controller 112 measures the time from the moment that the switch 108 switches to the voltage V until the voltage at node N₁ equals the high reference voltage VREF_(HI). When the comparator 110 switches states, the timer/controller causes the switch 108 to switch to ground and the combined capacitances (C and C_(t)) start discharging. If, for example, a person (106) is touching the dielectric 104 (or just in proximity to the conductive plate 102), then the effective capacitance C_(t) is relatively large, and the parallel combination of capacitances (C and C_(t)) charges relatively slowly. If there is no object 106 present, then the effective capacitance C_(t) is relatively small, and the parallel combination of capacitances (C and C_(t)) charges relatively rapidly.

FIG. 1B illustrates an example waveform at node N₁. At time t₀ the timer/controller 112 causes switch 108 to switch to the voltage V and the capacitances (C and C_(t)) chart charging. At time t₁, the voltage at node N₁ reaches the high reference voltage VREF_(HI) and the comparator 110 switches states. Also at time t₁, the timer/controller 112 causes switch 108 to switch to ground and the capacitances (C and C_(t)) start to discharge. At time t₂, the voltage at node N₁ reaches the low reference voltage VREF_(LO) and the timer/controller 112 starts another timing period (causes switch 108 to switch to voltage V).

The system 100 is subject to numerous accuracy limitations. First, electrical noise on node N₁ can affect when the comparator 110 switches states. Node N₁ may be affected by both radiated and conducted electrical noise. The conductive plate 102 may receive electrical noise from unintended electric fields and node N₁ may receive noise coupled from other electrical traces. In addition, node N₁ may be affected by electrical noise on the power supply lines and on the ground lines. If capacitive measurements are made periodically, then a particular concern is periodic noise having the same period as the measurements. Second, if the timer 112 is a digital counter counting clock pulses (CLK) then there is some inherent inaccuracy (resolution) in the digital measurement of time. Third, the resistance R and the capacitances C and C_(t) may vary with temperature and humidity.

As illustrated in the example of FIG. 1B, the rate of change of the voltage at node N₁ slows as the voltage at node N₁ increases towards the voltage V. If the high reference voltage VREF_(HI) is close to the voltage V, then there is a relatively long time during which the voltage at node N₁ is close to the high reference voltage VREF_(HI). Likewise, if the low reference voltage VREF_(LO) is close to ground, then there is a relatively long time during which the voltage at node N1 is close to the low reference voltage VREF_(LO). During the periods of time when the voltage at node N1 is close to one of the reference voltages (VREF_(HI), VREF_(LO)), a small amount of noise can cause the comparator 110 to switch states at an inappropriate time (or to not switch states at the appropriate time). One way to improve noise immunity for the system of FIG. 100 is to set the reference voltages (VREF_(HI), VREF_(LO)) at levels where the slope of the voltage at node N₁ is relatively high. For example, if VREF_(LO) is set to 0.2*V and if VREF_(HI) is set to 0.8*V, then the noise must be at least 0.2*V to cause the comparator 110 to switch states at an inappropriate time. These thresholds are depicted in FIG. 1B by VREF_(LO′) and VREF_(HI′).

For the example of FIG. 1A, the timer/controller 112 may measure the time for node N₁ to charge and/or discharge to the reference voltages (VREF_(HI), VREF_(LO)). Alternatively, the timer/controller 112 may measure the number of charge/discharge cycles that occur during a fixed period of time.

FIGS. 2A and 4A illustrate example systems with several improvements to the system 100 in FIG. 1A. One improvement is that at least one constant current source is used to charge and/or discharge the capacitances (C and C_(t)). This causes the capacitances to charge and/or discharge linearly instead of charging and discharging with a decreasing slope. Linear charging and discharging reduces the time that the input to the comparator 110 is close to one of the reference voltage thresholds (VREF_(HI), VREF_(LO)), and therefore reduces the time window in which the comparator 110 is sensitive to noise. In addition, a current source may overdrive some noise on node N₁. A second improvement is that the measurements may be controlled to be a-periodic even when the capacitance (parallel C and C_(t)) is constant. This reduces the effects of periodic noise. One method for making the measurements a-periodic is illustrated in FIG. 2D and a second method for making the measurements a-periodic is illustrated in FIGS. 4A and 4B. A third improvement is that noise on node N₁ may be measured to enable the system to compensate for noise, and/or to avoid measurements when the noise is too high, and/or to reject measurements that may have been subjected to unusual bursts of noise. A fourth improvement is to reject measurements that lie outside expected limits.

In FIG. 2A, elements having the same reference numbers as in FIG. 1A are all as described in conjunction with FIG. 1A. In the example system 200 of FIG. 2A, there are two current sources 202 and 204. At any given time, at most one of the current sources 202 and 204 is coupled to node N₁. As discussed in conjunction with FIGS. 2C and 2D, one current source 202 or 204 may be optional.

FIG. 2B illustrates an example waveform for node N₁ in FIG. 2A. At time t₀, the timer/controller 112 causes switch 108 to switch to current source 202 and the capacitances (C and C_(t)) start linearly charging. At time t₁, the voltage at node N₁ reaches the high reference voltage VREF_(HI) and the comparator 110 switches states. Also at time t₁, the timer/controller 112 causes switch 108 to switch to current source 204 and the capacitances (C and C_(t)) start to linearly discharge. At time t₂, the voltage at node N₁ reaches the low reference voltage VREF_(LO) and the timer/controller 112 starts another timing period (causes switch 108 to switch to current source 202). Note that linear charging and discharging reduces the time that the input to the comparator 110 is close to one of the reference voltage thresholds (VREF_(HI), VREF_(LO)), and therefore reduces the time window in which the comparator 110 is sensitive to noise.

FIG. 2C illustrates an example waveform for node N₁ for an alternative embodiment of the system 200 of FIG. 2A. For FIG. 2C, assume there is no current source 204 and instead, switch 108 couples node N₁ to current source 202 or to ground. For FIG. 2C, also assume that the timer/controller 112 determines the time at which each new timing period begins independent of when the voltage at node N1 falls to the low reference voltage VREF_(LO). At time t₀, the timer/controller 112 causes switch 108 to switch to current source 202 and the capacitances (C and C_(t)) start linearly charging. At time t₁, the voltage at node N₁ reaches the high reference voltage VREF_(HI) and the comparator 110 switches states. Also at time t₁, the timer/controller 112 causes switch 108 to switch to ground and the capacitances (C and C_(t)) start to discharge. At time t₂ the timer/controller 112 starts another timing period (causes switch 108 to switch to current source 202).

The voltage on node N₁ in FIG. 2A as depicted in FIG. 2C may be susceptible to noise having the same timing. In the example of FIG. 2C, the measurement time period from t₁ to t₂ is determined by the timer/controller 112. This measurement time period from t₁ to t₂ may be randomized by the timer/controller 112 to cause the time period for capacitance measurements to vary even when the capacitance (parallel C and C_(t)) is constant. For example, the timer controller 112 may generate a pseudo-random time period for the time from t₁ to t₂. Alternatively, the timer controller 112 may pseudo-randomly choose from two or more predetermined time periods. An example a-periodic waveform is illustrated in FIG. 2D. In FIG. 2D, the time period from t₁ to t₂ is not equal to the time period from t₃ to t₄. Note that in the examples of FIGS. 2C and 2D, charging is linear but discharging is non-linear (current source 202 but not current source 204). Alternatively, the system 200 may be configured so that discharging is linear and charging is non-linear (current source 204 but not current source 202) and the timer/controller 112 may vary the charging times. Alternatively, both charging and discharging may be linear or non-linear, and the timer/controller 112 may vary either the charging time period or the discharging time period.

The system 200 in FIG. 2A includes a noise measurement circuit 206. FIG. 3A illustrates additional detail for an example embodiment of the noise measurement circuit 206 in FIG. 2A. Only part of FIG. 2A is duplicated in FIG. 3A to facilitate illustration and discussion. In the example of FIG. 3A, the switch 108 is coupled to a rectifier circuit 300, followed by an integrator 302, followed by an analog-to-digital converter (ND) 304. The output of the A/D 304 is read by the timer/controller 112. The measurement circuit 206 may optionally be capacitively coupled (capacitor C_(c)). Assuming that resistance R (trace resistance) is small, the circuit of FIG. 3A effectively measures noise on node N₁ and integrates the noise over time. The ND 304 then provides a digital measure of that noise to the timer/controller 112. If the circuit of FIG. 3A is capacitively coupled (capacitor C_(c)), then the circuit of FIG. 3A measures AC noise, and may be used whether the switch 108 is switched or not-switched to one of the current sources (202, 204).

FIG. 3B illustrates additional detail for an alternative example embodiment of the noise measurement circuit 206 in FIG. 2A. Only part of FIG. 2A is duplicated in FIG. 3B to facilitate illustration and discussion. In the example of FIG. 3B, when the switch 108 is switched to current source 202, a known capacitance C₂ charges through a known resistance R₂. An A/D 306 measures the voltage on capacitance C₂ after a known period of time and the output of the A/D 306 is read by the timer/controller 112. Assuming that resistance R (trace resistance) is small relative to resistance R₂, the circuit of FIG. 3A effectively measures noise on node N₁. With calibration, the expected voltage on capacitance C₂ after the known period of time is known. If the actual voltage is significantly different than the expected voltage, the difference is assumed to be caused by noise.

For either example of noise measurement circuit 206, the noise measurement may be used change at least one capacitance measurement parameter. For example, the system 200 may determine that the noise is too great to initiate a capacitance measurement and the capacitance measurement may be deferred. Alternatively, the noise measurement may be used to determine whether a capacitance measurement is valid so capacitance measurements may be rejected if capacitance measurements are subject to excess noise. Alternatively, the reference voltages (VREF_(HI), VREF_(LO)) may be adjusted based on noise level. For example, VREF_(HI) may be adjusted closer to the supply voltage and VREF_(LO) may be adjusted closer to ground if the noise level is relatively low. Alternatively, the timer/controller 112 may have an expected range of charging time periods (for example, FIG. 2C, t₀ to t₁ and t₂-t₃) and the timer/controller 112 may reject measurements having a charging time period outside the expected range. The expected range may be reduced if the noise measurement circuit 206 indicates that noise is relatively low.

FIG. 4A illustrates an example embodiment of a system 400 that is an alternative embodiment of the system 200 of FIG. 2A, illustrating an alternative way of ensuring that the time period for capacitance measurements is variable even when the capacitance (parallel C and C_(t)) is constant. In FIG. 4A, elements having the same reference numbers as in FIGS. 1A and 2A are all as described in conjunction with FIGS. 1A and 2A. In the example of FIG. 4A, there are at least two current sources (402, 404) that may be coupled to node N₁ by switches (406, 408) controlled by the timer/controller 112. In the example of FIG. 4A, node N₁ is discharged by a switch 410 instead of by a current source to ground, but a current source to ground may optionally be used. The currents sourced by current sources 402 and 404 are not equal. Accordingly, the time periods required for node N₁ to charge to the high reference voltage VREF_(HI) are not equal because the currents provided by the different current sources are not equal. The timer/controller may select switches 406 and 408 in a pseudo-random sequence so that the voltage waveform on node N₁ is a-periodic even when the capacitance (parallel C and C_(t)) is constant. Alternatively, the system 400 may be configured so that a plurality of current sources are used to discharge, and the time periods required for node N₁ to discharge to the low reference voltage VREF_(LO) are made to be unequal.

FIG. 4B illustrates an example waveform on node N₁ of FIG. 4A. At time t₀, switch 406 switches current source 402 to node N₁ and the capacitances (C and C_(t)) linearly charge until the voltage at node N₁ equals the high reference voltage VREF_(HI). At time t₁, switch 410 is closed to discharge the capacitances. At time t₂, switch 410 opens and switch 408 closes to switch current source 404 to node N₁ and the capacitances (C and C_(t)) linearly charge until the voltage at node N₁ equals the high reference voltage VREF_(HI). Note that since current source 402 is not identical to current source 404, the time period from t₀ to t₁ is different than the time period from t₂ to t₃. Switches 406 and 408 are closed in a pseudo-random sequence so that the resulting voltage waveform on node N₁ is a-periodic.

FIG. 5 illustrates an example method 500 for capacitive sensing. Note, the particular order of steps as illustrated does not mean that the steps must be performed in the illustrated order, and some steps may be performed simultaneously. At step 502 a voltage at a node is changed. At step 504 a controller measures a capacitance at the node by measuring a time required for the node voltage to equal a predetermined threshold. At step 506 a noise measurement circuit measures electrical noise on the node. At step 508 the controller changes at least one capacitance measurement parameter in response to the measured noise.

Note that illustrating the timer/controller 112 as one functional unit is only to facilitate illustration and discussion, and the timing and controlling functions may be implemented by separate functional units. Likewise, illustration of the comparator 110, the timer/controller 112, the noise measurement circuit 206, the ND 304, and the ND 306 as separate functional units is only to facilitate illustration and discussion, and the timer/controller 112 may include any or all of the separately labeled functions.

While illustrative and presently preferred embodiments of the invention have been described in detail herein, it is to be understood that the inventive concepts may be otherwise variously embodied and employed and that the appended claims are intended to be construed to include such variations except insofar as limited by the prior art. 

What is claimed is:
 1. A circuit comprising: a variable capacitance device that includes a plate; a node coupled to the plate of the variable capacitance device; a first current source; a first charging switch coupled between the first current source and the node; a second current source; a second charging switch coupled between the second current source and the node, such that the first current source and the first charging switch are coupled in parallel with the second current source and the second charging switch; a discharge switch coupled between the node and a ground node; and a comparator coupled to the node.
 2. The circuit of claim 1 further comprising a controller coupled to the comparator and coupled to control the first charging switch, the second charging switch, and the discharge switch.
 3. The circuit of claim 2 further comprising a noise measurement circuit coupled to the node and having an output coupled to the controller.
 4. The circuit of claim 1, wherein the first charging switch, the second charging switch, and the discharge switch are coupled to the node by a resistor.
 5. The circuit of claim 1 further comprising a capacitor coupled between the node and the ground node.
 6. A circuit comprising: a variable capacitance device that includes a plate; a node coupled to the plate of the variable capacitance device; a charging circuit coupled to the node; a discharge switch coupled between the node and a ground node; and a controller coupled to the charging circuit and the discharge switch and configured to measure capacitance of the variable capacitance device by: causing the charging circuit to charge the variable capacitance device using a first current; thereafter, causing the discharge switch to discharge the variable capacitance device; causing the charging circuit to charge the variable capacitance device using a second current that is different from the first current; and thereafter, causing the discharge switch to discharge the variable capacitance device.
 7. The circuit of claim 6, wherein the charging circuit includes: a first current source to provide the first current; a first charging switch coupled between the first current source and the node; a second current source to provide the second current; and a second charging switch coupled between the second current source and the node.
 8. The circuit of claim 6 further comprising a noise measurement circuit coupled to the node and to the controller, wherein the controller is to determine a parameter used to measure the capacitance of the variable capacitance device based on an output of the noise measurement circuit.
 9. The circuit of claim 8 further comprising a comparator coupled to the node and having an output coupled to the controller, wherein: the comparator is coupled to receive a first reference voltage and a second reference voltage; and the parameter includes a magnitude of the first reference voltage and a magnitude of the second reference voltage.
 10. The circuit of claim 8, wherein the controller is to defer the measurement of the capacitance of the variable capacitance device based on the output of the noise measurement circuit.
 11. The circuit of claim 6, wherein the controller is to: cause the discharge switch to discharge the variable capacitance device for a first period of time following the charge of the variable capacitance device using the first current; and cause the discharge switch to discharge the variable capacitance device for a second period of time that is different from the first period of time following the charge of the variable capacitance device using the second current.
 12. The circuit of claim 11, wherein the controller is to determine the first period of time and the second period of time pseudo-randomly.
 13. The circuit of claim 6 further comprising a capacitor coupled between the node and the ground node.
 14. A method comprising: determining a capacitance of a variable capacitance device, wherein the determining includes: charging the variable capacitance device using a first current from a first current source; in response to the charging using the first current, discharging the variable capacitance device; charging the variable capacitance device using a second current from a second current source, wherein the first current and the second current are different in magnitude; and in response to the charging using the second current, discharging the variable capacitance device.
 15. The method of claim 14, wherein the charging of the variable capacitance device using the first current is performed for a first period and the charging of the variable capacitance device using the second current is performed for a second period that is different from the first period.
 16. The method of claim 14 further comprising deferring the determining of the capacitance of the variable capacitance device based on a noise measurement.
 17. The method of claim 14, wherein the discharging of the variable capacitance device in response to the charging using the first current is performed for a first period and the discharging of the variable capacitance device in response to the charging using the second current is performed for a second period that is different from the first period.
 18. The method of claim 17 further comprising pseudo-randomly determining the first period and the second period.
 19. The method of claim 14, wherein the charging of the variable capacitance device using the first current and the charging of the variable capacitance device using the second current includes comparing a voltage at a node to a reference voltage.
 20. The method of claim 19 further comprising determining the reference voltage based on a noise measurement. 